A commitment to innovation and sustainability
With Scarlet, spent your time in debugging, not creating the testbench. Try Scarlet for free, click link below!
Reduced Verification time
With Scarlet, complete UVM testbenches (including coverage and properties / assertions) can be generated in just a few minutes!
Save and Load testbenches!
Progress can be saved to be used later or be reused for another RTL.
Continuous Support
We will continue upgrading Scarlet with a lot of free updates, including support for RAL, UVM regressions and more!
AI models for SVA generation
Generate SystemVerilog Assertions with the help of AI with just selecting a file with English text OR selecting a Test Plan in Excel format.
Accesibility
No Verification experience is needed! Anyone can generate a complete UVM Testbench from scratch.
TCL generation for Formal tools
Create ready-to-go TCL files for common Formal tools like Jasper from Cadence (A Jasper License is still required and not included).
OS compatibility
Scarlet can be installed on Windows and Linux, differences between them can be found in User Guide document.
Scarlet internal Tools
Scarlet count with three main Tools: Specsium (UVM Testbench), Spectre (AI SVA generation) and Coverage (Coverage generation).
Specsium Tool
- Create a complete UVM Testbench in no time!
- Import SVA file from Spectre and Coverage tools.
- Simulate Testbenches out-of-the-box.
Spectre Tool
- Import Excel Test plans to generate SVA.
- Generate SVA from text files.
- Create SystemVerilog module file from the generated SVAs.
Coverage Tool
- Create coverpoints and covergroups easily.
- No experience in coverage is required.
- Generated coverage file can be imported in Specsium.
