SystemVerilog is both a Hardware Description Language (HDL) and a Hardware Verification Language (HVL), widely used in the digital IC design flow—especially in pre-silicon verification and also at the RTL design stage.
This course is designed for undergraduate and graduate electrical engineering students, as well as professionals in related fields, who want to build a strong foundation in SystemVerilog (SV) for careers in verification.
By the end of this course, you will be proficient in:
- Threads and Interprocess communication
- New data types used for simulation
- System Functions
- System Tasks
- Clocking Blocks
- Object Oriented Programming
- Functional Coverage
- Direct Programming Interface
- and more!
Start mastering SystemVerilog today and take the next step in your ASIC/IC verification career.
Course Instructor
Course Introduction
DV Tools – Questa
I. Installation
II. Project Management
III. Simulation
IV. Coverage Analysis
V. Assertion Analysis
I. Introduction to Verification
1.1 What is Verification?
1.2 Verification flow
II. Non-Synthesizable Data Types
2.1 Dynamic Arrays
2.2 Associative Arrays
2.3 Queues
2.4 Array reduction methods
2.5 Array ordering methods
2.6 Array locator methods
2.7 Unions
2.8 Strings
2.9 Constants
2.10 Chandle
2.11 Events
2.12 Time Values
III. Procedural Blocks
3.1 Initial
3.2 Final
IV. Procedural Statements
4.1 Repeat
4.2 Forever
Ex. Gate repeat stimulus
V. SystemVerilog Regions
5.1 How regions work?
5.2 Classification
VI. System Tasks
6.1 Simulation control
6.2 Severity control
6.3 Memory
6.4 File
6.5 Display
6.6 Trigonometric
6.7 PLA
VII. Compiler Directives
7.1 Definition
7.2 List of directives
VIII. Config
8.1 Introduction to Config blocks
8.2 Configuration syntax
8.3 Overriding parameters
IX. Clocking Blocks
9.1 Implementation
9.2 Clocking inputs
9.3 Clocking outputs
9.4 Default and global clocking
X. Checker
10.1 Creating a checker
10.2 Default clocking and disable
10.3 System functions
10.4 Free variable
XI. Program
11.1 What is a program?
11.2 Clocking blocks in programs
11.3 Reactive region behavior
XII. OOP
12.1 Introduction
12.2 Class definition and constructor
12.3 Static and protected
12.4 Inheritance
12.5 Virtual and pure
XIII. Randomization
13.1 How to randomize
Ex. ALU class random
Ex. ALU random stimulus
13.2 Constraints
13.3 Constraint operators
13.4 pre_randomize and post_randomize
13.5 randcase block
13.6 randsequence construct
Lab 1. ALU testbench with random stimulus
XIV. Threads & Processes communication
14.1 fork-join
Ex. ALU fork
14.2 Semaphore
14.3 Mailbox
Lab 2. ALU testbench with threads
Ex. ALU ref model
XV. Functional Coverage
15.1 What is coverage?
15.2 Covergroups and Coverpoints
15.3 Bins
15.4 Options
Ex. ALU Class coverage
XVI. Direct Programming Interface
16.1 Introduction
16.2 Import and Export
16.3 Pure and Context functions