Scarlet

SystemVerilog for Design

—

by

Scarlet

SystemVerilog is both a Hardware Description Language (HDL) and a Hardware Verification Language (HVL), widely used in the digital IC design flow—especially in pre-silicon verification and also at the RTL design stage.

This course is designed for undergraduate and graduate electrical engineering students, as well as professionals in related fields, who want to build a strong foundation in SystemVerilog (SV) for careers in IC design.

By the end of this course, you will be proficient in:

  • SystemVerilog Data Types
  • SV Operators
  • SV Packages
  • SV Interfaces
  • Procedural blocks
  • Procedural statements
  • Tasks and Functions
  • Arrays, Structures, Unions
  • and more!

Start mastering SystemVerilog today and take the next step in your ASIC/IC design career.

Course Information

Difficulty: Beginner

Categories:

Course Instructor

Scarlet Scarlet Author

Course Introduction

Introduction to the Course
Lesson 1 of 1 within section Course Introduction.
0

DV Tools – Vivado

I. Installation
Lesson 1 of 4 within section DV Tools – Vivado.
0
II. Project Management
Lesson 2 of 4 within section DV Tools – Vivado.
0
III. Simulation
Lesson 3 of 4 within section DV Tools – Vivado.
0
IV. Report Generation
Lesson 4 of 4 within section DV Tools – Vivado.
0

I. Introduction to SystemVerilog Basics

1.1 What is digital design?
Lesson 1 of 5 within section I. Introduction to SystemVerilog Basics.
0
1.2 RTL and HDL
Lesson 2 of 5 within section I. Introduction to SystemVerilog Basics.
0
1.3 What is SystemVerilog?
Lesson 3 of 5 within section I. Introduction to SystemVerilog Basics.
0
1.4 Modules and Ports
Lesson 4 of 5 within section I. Introduction to SystemVerilog Basics.
0
1.5 Guidelines
Lesson 5 of 5 within section I. Introduction to SystemVerilog Basics.
0
Has Quiz

II. SystemVerilog Data Types

2.1 Variables and Nets
Lesson 1 of 5 within section II. SystemVerilog Data Types.
0
2.2 4-State and 2-State Data Types
Lesson 2 of 5 within section II. SystemVerilog Data Types.
0
2.3 User defined data types
Lesson 3 of 5 within section II. SystemVerilog Data Types.
0
2.4 Enumerated Types
Lesson 4 of 5 within section II. SystemVerilog Data Types.
0
2.5 Signed and Unsigned
Lesson 5 of 5 within section II. SystemVerilog Data Types.
0
Has Quiz

III. Operators

3.1 Legacy operators
Lesson 1 of 7 within section III. Operators.
0
Lab 1. Logical gates with operators
Lesson 2 of 7 within section III. Operators.
0
3.2 New operators
Lesson 3 of 7 within section III. Operators.
0
Lab 2. Multiplexer in cascade
Lesson 4 of 7 within section III. Operators.
0
3.3 Casting
Lesson 5 of 7 within section III. Operators.
0
Has Quiz
Lab 3. Comparators
Lesson 6 of 7 within section III. Operators.
0
Ex. Minimum
Lesson 7 of 7 within section III. Operators.
0

IV. Structures

4.1 Declaration and assigning
Lesson 1 of 3 within section IV. Structures.
0
4.2 Packed and Unpacked structures
Lesson 2 of 3 within section IV. Structures.
0
4.3 Passing structure’s data
Lesson 3 of 3 within section IV. Structures.
0
Has Quiz

V. Unions

5.1 Unpacked unions
Lesson 1 of 3 within section V. Unions.
0
5.2 Tagged unions
Lesson 2 of 3 within section V. Unions.
0
5.3 Packed unions
Lesson 3 of 3 within section V. Unions.
0
Has Quiz

VI. Arrays

6.1 Unpacked arrays
Lesson 1 of 6 within section VI. Arrays.
0
6.2 Packed arrays
Lesson 2 of 6 within section VI. Arrays.
0
6.3 Array initialization
Lesson 3 of 6 within section VI. Arrays.
0
6.4 Assignments in arrays
Lesson 4 of 6 within section VI. Arrays.
0
6.5 User defined types and arrays
Lesson 5 of 6 within section VI. Arrays.
0
6.6 Array querying system functions
Lesson 6 of 6 within section VI. Arrays.
0
Has Quiz

VII. Packages

7.1 What is a package?
Lesson 1 of 2 within section VII. Packages.
0
7.2 Access to content
Lesson 2 of 2 within section VII. Packages.
0
Has Quiz

VIII. Procedural Blocks, Tasks and Functions

8.1 Always block
Lesson 1 of 5 within section VIII. Procedural Blocks, Tasks and Functions.
0
8.2 Combinational block
Lesson 2 of 5 within section VIII. Procedural Blocks, Tasks and Functions.
0
8.3 Latched blocks
Lesson 3 of 5 within section VIII. Procedural Blocks, Tasks and Functions.
0
8.4 Sequential blocks
Lesson 4 of 5 within section VIII. Procedural Blocks, Tasks and Functions.
0
8.5 Tasks and Functions
Lesson 5 of 5 within section VIII. Procedural Blocks, Tasks and Functions.
0
Has Quiz

IX. Procedural Statements

9.1 For Loop
Lesson 1 of 12 within section IX. Procedural Statements.
0
9.2 While Loop
Lesson 2 of 12 within section IX. Procedural Statements.
0
9.3 If Condition
Lesson 3 of 12 within section IX. Procedural Statements.
0
Ex. Min Array
Lesson 4 of 12 within section IX. Procedural Statements.
0
Ex. Shift Register
Lesson 5 of 12 within section IX. Procedural Statements.
0
Ex. Register with Multiple Format
Lesson 6 of 12 within section IX. Procedural Statements.
0
9.4 Case Statement
Lesson 7 of 12 within section IX. Procedural Statements.
0
Has Quiz
Ex. Bus Control
Lesson 8 of 12 within section IX. Procedural Statements.
0
Ex. Demux
Lesson 9 of 12 within section IX. Procedural Statements.
0
Lab 4. Arithmetic Logic Unit
Lesson 10 of 12 within section IX. Procedural Statements.
0
Lab 5. Counter (binary)
Lesson 11 of 12 within section IX. Procedural Statements.
0
Lab 6. Shift Register (bidirectional)
Lesson 12 of 12 within section IX. Procedural Statements.
0

X. Finite State Machine

10.1 Introduction
Lesson 1 of 4 within section X. Finite State Machine.
0
10.2 Moore FSM
Lesson 2 of 4 within section X. Finite State Machine.
0
10.3 Mealy FSM
Lesson 3 of 4 within section X. Finite State Machine.
0
Has Quiz
10.4 Tips to design an FSM
Lesson 4 of 4 within section X. Finite State Machine.
0

XI. SystemVerilog Interfaces

11.1 What is an Interface?
Lesson 1 of 2 within section XI. SystemVerilog Interfaces.
0
11.2 Construction and Implementation
Lesson 2 of 2 within section XI. SystemVerilog Interfaces.
0
Has Quiz

XII. Generate

12.1 Loop Generate
Lesson 1 of 2 within section XII. Generate.
0
12.2 Conditional Generate
Lesson 2 of 2 within section XII. Generate.
0
Has Quiz

Sapphire Membership Required

You must be a Sapphire member to access this content.

Join Now

Already a member? Log in here