SystemVerilog Assertions (SVA) are a powerful set of directives used to validate and test design specifications. They play a key role in UVM-based functional verification and formal verification, but can also be applied during the design stage to ensure correctness and reliability.
This course is designed for undergraduate and graduate electrical engineering students, as well as professionals in related fields, who want to gain practical expertise in SVA for careers in functional or formal ASIC verification.
By the end of this course, you will be able to confidently apply SystemVerilog Assertions in real-world verification environments, strengthening your skill set for the semiconductor industry.
In this course you will learn:
- Assertions Layers
- SVA Directives
- Concurrent Assertions
- Immediate Assertions
- SVA Operators
- SVA System Tasks
- Guidelines
- and more!
Course Instructor
Course Introduction
I. Introduction to Assertions
1.1 What is an assertion?
1.2 Structure of an assertion
1.3 Where should assertions be declared?
1.4 Assertion-Based Verification
II. Sequences
2.1 Definition
2.2 Repetition operators
2.3 Sequences operators
2.4 Methods
2.5 Events, arguments and variables
Lab 1. Creating Sequences for a BRAM
III. Properties
3.1 Syntax
3.2 Arguments and variables
3.3 Clocking events
3.4 Disable
3.5 Property operators
3.6 System functions
3.7 System tasks
3.8 Multiple clocks
Lab 2. Creating Properties for a BRAM
IV. Assertions
4.1 Syntax
4.2 Concurrent assertions
Ex. Tasks and Properties
Ex. Clock Divider
Ex. Multiplier Accumulator
4.3 Immediate assertions
4.4 Binding assertions
Lab 3. Creating Assertions for a BRAM
Ex. UART
Lab 4. Creating Assertions for a Counter
Ex. I2C
V. Guidelines
5.1 Naming
5.2 Properties
5.3 Assertions