The Universal Verification Methodology or UVM for short, is a class library for functional verification that grants reusability and a more robust testbench that allows coverage gathering, SVA for testing specifications, random stimulus and advance reporting.
This course is focused to graduate or undergraduate electrical engineer students or any related area that wants to learn UVM for any ASIC Functional Verification related job position.
In this course you will learn:
- How to build an UVM Testbench
- Strategies and Guidelines
- UVM Library Class
- Functional Verification Flow
- Verification Plan
- Test Plan
- and more!
Course Instructor
Course Introduction
I. Introduction to Functional Verification
1.1 What is functional verification?
1.2 Functional verification Flow
1.3 What is UVM?
II. UVM Components
2.1 Testbench
2.2 Test
2.3 Environment
2.4 Scoreboard
2.5 Agent
2.6 Monitor
2.7 Subscriber
2.8 Driver
2.9 Sequencer
2.10 Sequence
III. Creating Components
3.1 Factory definition
3.2 UVM Phases
3.3 Components creation
IV. Connection between components
4.1 TLM Introduction
4.2 Port, Export and Imp connections
4.3 Agent connections
4.4 Environment connections
V. Sequences
5.1 Driver-Sequencer Handshake
5.2 Creating a sequence
5.3 Multiple sequences
5.4 Virtual sequence
5.5 Virtual sequencer
5.6 Executing sequence on test
Ex. BRAM testbench – No Virtual Sequencer
Ex. BRAM testbench – With Virtual Sequencer
Ex. BRAM testbench – Two Agents
Ex. BRAM testbench – Two Environments
5.7 Configurable sequences
Lab 1. Coverage in UVM Testbench
VI. Configurable Objects
6.1 Creation of Objects
6.2 Configuring the test
6.3 Configuring the environment
6.4 Configuring the agent
VII. Report Macros
7.1 Basic messaging
7.2 Message element
7.3 Message trace
VIII. Container Classes
8.1 uvm_queue
8.2 uvm_pool
IX. Synchronization Classes
9.1 uvm_event
9.2 uvm_event_callback
9.3 uvm_barrier
9.4 uvm_objection
9.5 uvm_heartbeat
X. Comparators
10.1 In order comparator
10.2 Algorithmic comparator
XI. Callbacks
11.1 Definition
11.2 Adding callbacks
XII. Agent classification
12.1 Classification
12.2 Reactive agent
XIII. Register Abstraction Layer
13.1 Introduction to RAL
13.2 Backdoor Access
13.3 Frontdoor Access
XIV. Assertions
14.1 Assertions vs Scoreboard
14.2 How to include assertions?
Lab 2. Assertions in UVM Testbench
XV. Verification Plan
15.1 What is a verification plan?
15.2 General template
15.3 Tools to track progress
Lab 3. Creating a test plan for a BRAM testbench
Lab 4. Creating a UVM testbench for an AXI4 lite Slave