Scarlet

Mixed-Signal Modeling with Verilog-AMS

—

by

Scarlet

Verilog-AMS is a hardware description language used to model and simulate both analog and digital systems within a single environment. It extends traditional Verilog by adding analog and continuous-time behavioral modeling capabilities, allowing engineers to describe mixed-signal circuits more efficiently.

Verilog-AMS is especially important in the design and verification of modern integrated circuits that combine digital logic with analog components, such as:

  • data converters (ADCs/DACs)
  • PLLs
  • sensors
  • power management circuits
  • high-speed communication interfaces

One of its main advantages is that it enables behavioral modeling of complex analog blocks, significantly reducing simulation time compared to full transistor-level simulations. This allows designers and verification engineers to validate system functionality earlier in the development process.

In industry, Verilog-AMS is commonly applied in mixed-signal verification flows, system-level modeling, and the creation of reusable analog behavioral models for simulation and testing environments.

This course is focused to graduate or undergraduate electrical engineer students or any related area that wants to learn Verilog-AMS for any Analog or Mixed-Signal Verification related job position.

In this course you will learn:

  • Verilog-A for analog modeling
  • How to model mixed-signal blocks with Verilog-AMS
  • New data types introduced by Verilog-A(MS)
  • Procedural blocks and statements for analog and mixed-signal logic
  • Analog events and mixed-signal processes synchronization
  • New Operators and System Tasks and Functions for analog behavior
  • and more!

Course Information

Difficulty: Advanced

Categories:

Course Instructor

Scarlet Scarlet Author

Course Introduction

Introduction to the Course
Lesson 1 of 1 within section Course Introduction.
0

DV Tools – SMASH

I. Installation
Lesson 1 of 3 within section DV Tools – SMASH.
0
II. Project Management
Lesson 2 of 3 within section DV Tools – SMASH.
0
III. Simulation
Lesson 3 of 3 within section DV Tools – SMASH.
0

I. Introduction to Verilog-AMS

1.1 Mixed-Signal IC Circuits
Lesson 1 of 4 within section I. Introduction to Verilog-AMS.
0
1.2 Verilog-AMS background
Lesson 2 of 4 within section I. Introduction to Verilog-AMS.
0
1.3 Differences with (System)Verilog
Lesson 3 of 4 within section I. Introduction to Verilog-AMS.
0
1.4 Verilog-AMS File Overview
Lesson 4 of 4 within section I. Introduction to Verilog-AMS.
0
Has Quiz

II. Analog Procedural Block

2.1 Analog Block
Lesson 1 of 2 within section II. Analog Procedural Block.
0
2.2 Analog Initial Block
Lesson 2 of 2 within section II. Analog Procedural Block.
0
Has Quiz

III. Data Types

3.1 Legacy Data Types
Lesson 1 of 5 within section III. Data Types.
0
3.2 wreal Data Type
Lesson 2 of 5 within section III. Data Types.
0
3.3 Output variables
Lesson 3 of 5 within section III. Data Types.
0
3.4 Disciplines
Lesson 4 of 5 within section III. Data Types.
0
3.5 Ground declaration
Lesson 5 of 5 within section III. Data Types.
0
Has Quiz

IV. Analog Signals

4.1 Access Functions
Lesson 1 of 5 within section IV. Analog Signals.
0
4.2 Port Access
Lesson 2 of 5 within section IV. Analog Signals.
0
4.3 Net and Branch Access
Lesson 3 of 5 within section IV. Analog Signals.
0
4.4 Switch Branch
Lesson 4 of 5 within section IV. Analog Signals.
0
Has Quiz
Lab 1. Relay with Load
Lesson 5 of 5 within section IV. Analog Signals.
0

V. Analog Operators

5.1 Introduction
Lesson 1 of 20 within section V. Analog Operators.
0
5.2 Legacy Operators
Lesson 2 of 20 within section V. Analog Operators.
0
5.3 Direct Contribution Operator
Lesson 3 of 20 within section V. Analog Operators.
0
5.4 Indirect Contribution Operator
Lesson 4 of 20 within section V. Analog Operators.
0
5.5 ddt Operator
Lesson 5 of 20 within section V. Analog Operators.
0
Ex. Passive High-Pass Filter
Lesson 6 of 20 within section V. Analog Operators.
0
Ex. Passive Low-Pass Filter
Lesson 7 of 20 within section V. Analog Operators.
0
5.6 idt Operator
Lesson 8 of 20 within section V. Analog Operators.
0
Ex. Inductor
Lesson 9 of 20 within section V. Analog Operators.
0
5.7 idtmod Operator
Lesson 10 of 20 within section V. Analog Operators.
0
5.8 idx Operator
Lesson 11 of 20 within section V. Analog Operators.
0
Ex. Diode
Lesson 12 of 20 within section V. Analog Operators.
0
5.9 absdelay Operator
Lesson 13 of 20 within section V. Analog Operators.
0
5.10 transition Operator
Lesson 14 of 20 within section V. Analog Operators.
0
5.11 slew Operator
Lesson 15 of 20 within section V. Analog Operators.
0
5.12 last_crossing Operator
Lesson 16 of 20 within section V. Analog Operators.
0
5.13 limexp Operator
Lesson 17 of 20 within section V. Analog Operators.
0
5.14 Laplace Operators
Lesson 18 of 20 within section V. Analog Operators.
0
5.15 Z-transform Operators
Lesson 19 of 20 within section V. Analog Operators.
0
Has Quiz
Lab 2. Laplace Filters
Lesson 20 of 20 within section V. Analog Operators.
0

VI. Procedural Statements

6.1 Conditional Statements
Lesson 1 of 4 within section VI. Procedural Statements.
0
6.2 Loop Statements
Lesson 2 of 4 within section VI. Procedural Statements.
0
Has Quiz
Ex. Multiple analog signals
Lesson 3 of 4 within section VI. Procedural Statements.
0
Ex. ADC
Lesson 4 of 4 within section VI. Procedural Statements.
0

VII. Analog Event Control

7.1 Introduction
Lesson 1 of 5 within section VII. Analog Event Control.
0
7.2 Global events
Lesson 2 of 5 within section VII. Analog Event Control.
0
7.3 Monitored events
Lesson 3 of 5 within section VII. Analog Event Control.
0
Ex. DAC
Lesson 4 of 5 within section VII. Analog Event Control.
0
7.4 Named events
Lesson 5 of 5 within section VII. Analog Event Control.
0
Has Quiz

VIII. Parameters

8.1 Value range specification
Lesson 1 of 8 within section VIII. Parameters.
0
Ex. OpAmp
Lesson 2 of 8 within section VIII. Parameters.
0
Ex. Active Low-Pass Filter
Lesson 3 of 8 within section VIII. Parameters.
0
Ex. Active High-Pass Filter
Lesson 4 of 8 within section VIII. Parameters.
0
Lab 3. Inverting Amplifier
Lesson 5 of 8 within section VIII. Parameters.
0
Lab 4. Non-Inverting Amplifier
Lesson 6 of 8 within section VIII. Parameters.
0
8.2 Parameter aliases
Lesson 7 of 8 within section VIII. Parameters.
0
8.3 Paramsets
Lesson 8 of 8 within section VIII. Parameters.
0
Has Quiz

IX. Generate Construct

9.1 Loop generate
Lesson 1 of 6 within section IX. Generate Construct.
0
Ex. RC Ladder
Lesson 2 of 6 within section IX. Generate Construct.
0
Lab 5. Adder
Lesson 3 of 6 within section IX. Generate Construct.
0
Lab 6. Subtracter
Lesson 4 of 6 within section IX. Generate Construct.
0
9.2 Conditional generate
Lesson 5 of 6 within section IX. Generate Construct.
0
Has Quiz
Ex. Comparator
Lesson 6 of 6 within section IX. Generate Construct.
0

X. Simulation Cycle

10.1 Analog analysis
Lesson 1 of 5 within section X. Simulation Cycle.
0
Ex. Sweep Analysis
Lesson 2 of 5 within section X. Simulation Cycle.
0
10.2 System Initialization
Lesson 3 of 5 within section X. Simulation Cycle.
0
10.3 Analog simulation cycle
Lesson 4 of 5 within section X. Simulation Cycle.
0
10.4 Mixed-signal simulation cycle
Lesson 5 of 5 within section X. Simulation Cycle.
0
Has Quiz

XI. Analog Functions

11.1 Analysis
Lesson 1 of 8 within section XI. Analog Functions.
0
11.2 AC stimulus
Lesson 2 of 8 within section XI. Analog Functions.
0
Ex. Differentiator
Lesson 3 of 8 within section XI. Analog Functions.
0
Ex. Integrator
Lesson 4 of 8 within section XI. Analog Functions.
0
11.3 Noise
Lesson 5 of 8 within section XI. Analog Functions.
0
Ex. Diode noise
Lesson 6 of 8 within section XI. Analog Functions.
0
Ex. Digital noise
Lesson 7 of 8 within section XI. Analog Functions.
0
11.4 User-defined functions
Lesson 8 of 8 within section XI. Analog Functions.
0
Has Quiz

XII. Mixed-Signal

12.1 Introduction
Lesson 1 of 5 within section XII. Mixed-Signal.
0
12.2 Accessing A/D Nets
Lesson 2 of 5 within section XII. Mixed-Signal.
0
12.3 A/D events
Lesson 3 of 5 within section XII. Mixed-Signal.
0
12.4 Connect modules
Lesson 4 of 5 within section XII. Mixed-Signal.
0
Has Quiz
Ex. DAC – ADC
Lesson 5 of 5 within section XII. Mixed-Signal.
0

XIII. System Tasks and Functions

13.1 Legacy System Tasks and Functions
Lesson 1 of 11 within section XIII. System Tasks and Functions.
0
Ex. QAM
Lesson 2 of 11 within section XIII. System Tasks and Functions.
0
13.2 Analog Kernel Parameter
Lesson 3 of 11 within section XIII. System Tasks and Functions.
0
13.3 Dynamic Simulation Probe
Lesson 4 of 11 within section XIII. System Tasks and Functions.
0
13.4 Analog Kernel Control
Lesson 5 of 11 within section XIII. System Tasks and Functions.
0
13.5 Hierarchical Parameter
Lesson 6 of 11 within section XIII. System Tasks and Functions.
0
13.6 Explicit Binding Detection
Lesson 7 of 11 within section XIII. System Tasks and Functions.
0
13.7 Analog Node Alias
Lesson 8 of 11 within section XIII. System Tasks and Functions.
0
13.8 Table Based Interpolation
Lesson 9 of 11 within section XIII. System Tasks and Functions.
0
13.9 Connectmodule Access
Lesson 10 of 11 within section XIII. System Tasks and Functions.
0
13.10 Connectmodule Supplementary Access
Lesson 11 of 11 within section XIII. System Tasks and Functions.
0
Has Quiz

XIV. Compiler Directives

14.1 Legacy Compiler Directives
Lesson 1 of 3 within section XIV. Compiler Directives.
0
14.2 Default Discipline
Lesson 2 of 3 within section XIV. Compiler Directives.
0
14.3 Default Transition
Lesson 3 of 3 within section XIV. Compiler Directives.
0
Has Quiz

XV. Verilog-A Language

15.1 Verilog-A Overview
Lesson 1 of 6 within section XV. Verilog-A Language.
0
15.2 Verilog-A Limitations
Lesson 2 of 6 within section XV. Verilog-A Language.
0
Has Quiz
Ex. Device Model
Lesson 3 of 6 within section XV. Verilog-A Language.
0
Ex. SPICE Model
Lesson 4 of 6 within section XV. Verilog-A Language.
0
Lab 7. CVC
Lesson 5 of 6 within section XV. Verilog-A Language.
0
Lab 8. VCC
Lesson 6 of 6 within section XV. Verilog-A Language.
0

Sapphire Membership Required

You must be a Sapphire member to access this content.

Join Now

Already a member? Log in here